Device Structure
/ W. ^1 D7 }, T◆ CMOS image sensor
% x* U% u% E+ [6 ]$ \ w◆ Image size Diagonal 11.1 mm (Type 2/3) Approx. 5.07 M pixels All-pixel Diagonal 7.7 mm (Type 1/2.35) Approx. 2.11 M pixels 1080p-Full HD ' z5 @4 G8 y0 }& S& v
◆ Total number of pixels 2464 (H) × 2066 (V) Approx. 5.09 M pixels
2 z( C- P x7 K* T◆ Number of effective pixels 2464 (H) × 2056 (V) Approx. 5.07 M pixels 2 L' ]* e% w2 H) x: M- p
◆ Number of active pixels 2464 (H) × 2056 (V) Approx. 5.07 M pixels
* k% q$ a4 H% E, U" [9 V◆ Number of recommended recording pixels 2448 (H) × 2048 (V) Approx. 5.01 M pixels All-pixel 1920 (H) × 1080 (V) Approx. 2.07 M pixels 1080p-Full HD * X7 @, |, a5 o4 x
◆ Unit cell size 3.45 µm (H) × 3.45 µm (V) * B* M# w c+ `) r
◆ Optical black Horizontal (H) direction: Front 0 pixels, rear 0 pixels Vertical (V) direction: Front 10 pixels, rear 0 pixels % S3 w6 b n* Q# z( R
◆ Substrate material Silicon) e, z1 Q) P: W5 F
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Features
5 x0 y. v; O. X: g. i◆ CMOS active pixel type dots
$ `/ t0 H/ L H5 a◆ Built-in timing adjustment circuit, H/V driver and serial communication circuit 3 y+ e# @5 O, T) p
◆ Global shutter function
0 w' m% x1 L$ T# E% z◆ Input frequency 37.125 MHz / 74.25 MHz / 54MHz
n% m" {, l( @; w' I" n8 F9 f/ B+ g◆ Number of recommended recording pixels: 2448 (H) × 2048 (V) approx. 5.01 M pixels , J ~5 m. d4 C" \. B* Q1 }' p
Readout mode
- d5 M7 h: b5 G7 sAll-pixel scan mode 3 Q( s) |8 z% j5 q" B
1080p-Full HD readout mode ) B7 n7 W1 u) y
Vertical / Horizontal 1 / 2 Subsampling mode ! }! {9 K$ B7 _, x
Vertical 2-pixel FD Binning mode ROI mode / d. b9 D5 i- z; E
Vertical / Horizontal‐Normal / Inverted readout mode
5 Z# W( H0 [3 m◆ Readout rate
H6 J0 ~ _, F3 L1 S$ | @( tMaximum frame rate in
& ~8 h5 q) a8 ]2 H+ HAll-pixel scan mode: 8 bit 163.4 frame/s, 10 bit:144.7 frame/s, 12 bit:89.5 frame/s 1 r d8 a0 d5 D+ X6 W: D
◆ Variable-speed shutter function (resolution 1 H units) ( w$ F% Z Q |; \
◆ 8-bit / 10-bit / 12-bit A/D converter 4 e9 ?- F2 a9 e- f& C
◆ CDS / PGA function 0 dB to 24 dB: Analog Gain (0.1 dB step) 24.1 dB to 48 dB: Analog Gain: 24 dB + Digital Gain: 0.1 dB to 24 dB (0.1 dB step)
8 [, T' B% E: T: A+ ?8 c◆ I/O interface Low voltage LVDS (150 mVp-p) serial (4 ch / 8 ch / 16ch switching) DDR output 1 h( b2 ?9 t8 O2 W; s$ g E$ J8 R
◆ Recommended lens F number: 2.8 or more (Close side)
& c, r4 b, t c6 C0 R& f3 B( W◆ Recommended exit pupil distance: –100 mm to –∞" n; G1 U9 n/ k
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|Shenzhen Lianshi Electronics Co., Ltd
( 粤ICP备13003189号 )
发表于 2022-3-29 21:22:13