Device Structure ; U8 Y7 {6 B8 @( H/ |' K9 I* C' M9 [
◆ CMOS image sensor
5 J" N, E& @& |8 P◆ Image size Diagonal 11.1 mm (Type 2/3) Approx. 5.07 M pixels All-pixel Diagonal 7.7 mm (Type 1/2.35) Approx. 2.11 M pixels 1080p-Full HD 4 R6 {8 h( |) k2 l5 ^! R8 _
◆ Total number of pixels 2464 (H) × 2066 (V) Approx. 5.09 M pixels
/ v$ h9 Z8 D. Q X: _! }◆ Number of effective pixels 2464 (H) × 2056 (V) Approx. 5.07 M pixels 6 A+ ^8 r" Q* i7 L; W$ |1 w" {# }
◆ Number of active pixels 2464 (H) × 2056 (V) Approx. 5.07 M pixels 9 S) y& n, R. ]8 D% u
◆ Number of recommended recording pixels 2448 (H) × 2048 (V) Approx. 5.01 M pixels All-pixel 1920 (H) × 1080 (V) Approx. 2.07 M pixels 1080p-Full HD 7 v( H) K1 I9 c2 t1 ?6 H
◆ Unit cell size 3.45 µm (H) × 3.45 µm (V) $ m, s1 j; l5 h0 p1 @
◆ Optical black Horizontal (H) direction: Front 0 pixels, rear 0 pixels Vertical (V) direction: Front 10 pixels, rear 0 pixels , H, d; `1 b6 [# }- |/ V4 S
◆ Substrate material Silicon; {1 V. y# z& {, e$ C5 h
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Features 7 `( C; E# H0 _/ ^
◆ CMOS active pixel type dots ' e! S8 L+ I1 a/ i) b6 M
◆ Built-in timing adjustment circuit, H/V driver and serial communication circuit ' X7 {) m- y, Q3 ~) b2 Y
◆ Global shutter function
8 O% m$ s% }3 P0 v9 E◆ Input frequency 37.125 MHz / 74.25 MHz / 54MHz , q% h8 }! V8 s I
◆ Number of recommended recording pixels: 2448 (H) × 2048 (V) approx. 5.01 M pixels
+ u: K5 h. O8 {3 H6 I' P5 y/ H3 cReadout mode + R4 o% I8 E m; g: g( E
All-pixel scan mode
2 ]/ @6 C; T5 @+ ?& X; M. F; S1080p-Full HD readout mode
7 {9 y- r' C% ~! L( fVertical / Horizontal 1 / 2 Subsampling mode
! v) H! H/ q( j; {/ D, [Vertical 2-pixel FD Binning mode ROI mode
' i4 s6 P+ {& c0 P' ~3 W, {Vertical / Horizontal‐Normal / Inverted readout mode 2 ^6 W. m2 O8 M
◆ Readout rate 6 g! \( N6 Z! g) W5 }. A
Maximum frame rate in
, A- n2 u5 A; Y+ m/ @# ~' BAll-pixel scan mode: 8 bit 163.4 frame/s, 10 bit:144.7 frame/s, 12 bit:89.5 frame/s 8 N0 \; Z7 K: e
◆ Variable-speed shutter function (resolution 1 H units) ) i* k9 p: v7 E3 `! X" Z) H
◆ 8-bit / 10-bit / 12-bit A/D converter 3 f" E, T" } O2 W
◆ CDS / PGA function 0 dB to 24 dB: Analog Gain (0.1 dB step) 24.1 dB to 48 dB: Analog Gain: 24 dB + Digital Gain: 0.1 dB to 24 dB (0.1 dB step)
0 t$ |- G8 R6 {; m8 a◆ I/O interface Low voltage LVDS (150 mVp-p) serial (4 ch / 8 ch / 16ch switching) DDR output ' y# L S+ K4 k7 E
◆ Recommended lens F number: 2.8 or more (Close side) % d O* M0 w9 h1 ^3 Z4 s' V! Y
◆ Recommended exit pupil distance: –100 mm to –∞
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|Shenzhen Lianshi Electronics Co., Ltd
( 粤ICP备13003189号 )
发表于 2022-3-29 21:22:13