Device Structure F1 x% r# h4 V5 B
◆ CMOS image sensor
$ {( F. T+ |5 n: } n" g" f◆ Image size Diagonal 11.1 mm (Type 2/3) Approx. 5.07 M pixels All-pixel Diagonal 7.7 mm (Type 1/2.35) Approx. 2.11 M pixels 1080p-Full HD
}5 B, x' }+ p) `; Z# `; ?! @◆ Total number of pixels 2464 (H) × 2066 (V) Approx. 5.09 M pixels
+ L5 d9 I/ i$ ~/ p/ v% w◆ Number of effective pixels 2464 (H) × 2056 (V) Approx. 5.07 M pixels $ r) v% }1 X7 I3 Y1 h" b
◆ Number of active pixels 2464 (H) × 2056 (V) Approx. 5.07 M pixels 7 v, k$ O/ y& Y1 ]/ O& O% X/ q8 y; E
◆ Number of recommended recording pixels 2448 (H) × 2048 (V) Approx. 5.01 M pixels All-pixel 1920 (H) × 1080 (V) Approx. 2.07 M pixels 1080p-Full HD
% @) p, z; y) |; b+ v9 x+ Q◆ Unit cell size 3.45 µm (H) × 3.45 µm (V) , D1 ]) ?/ N1 }! g0 n- {
◆ Optical black Horizontal (H) direction: Front 0 pixels, rear 0 pixels Vertical (V) direction: Front 10 pixels, rear 0 pixels
. H+ k% f" Q# y- H) n2 G% n- R◆ Substrate material Silicon
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$ Y' i, Z6 m* g; SFeatures ! L/ E b t; Y- W* N$ X
◆ CMOS active pixel type dots
* T- p ?2 ~5 e! W7 x$ u◆ Built-in timing adjustment circuit, H/V driver and serial communication circuit
8 I/ N) T5 `+ r$ Q0 Z" T◆ Global shutter function ! o& p& N; C* `$ |: }( R
◆ Input frequency 37.125 MHz / 74.25 MHz / 54MHz
5 `& s3 d s5 E( Q& h7 Y◆ Number of recommended recording pixels: 2448 (H) × 2048 (V) approx. 5.01 M pixels
8 F5 \% Z3 L# H( i$ U) b3 t' H* l- B! MReadout mode 1 F$ q3 c9 q* C J
All-pixel scan mode
+ ~' t4 a4 d- B3 N# p# u3 s1080p-Full HD readout mode
4 f, o# G% H" L5 kVertical / Horizontal 1 / 2 Subsampling mode
9 E- Z& }. A% E" @! |; R! QVertical 2-pixel FD Binning mode ROI mode
4 a+ G* Q7 ], {4 T8 K. i( OVertical / Horizontal‐Normal / Inverted readout mode 0 L4 T8 W2 o% L3 v/ A4 m
◆ Readout rate 2 L1 A" z' D. w# d& d
Maximum frame rate in
g, S7 Z0 v( l5 a* q' `# u$ A3 ]All-pixel scan mode: 8 bit 163.4 frame/s, 10 bit:144.7 frame/s, 12 bit:89.5 frame/s
) g8 {, V: L6 V! \. A/ a◆ Variable-speed shutter function (resolution 1 H units)
1 q4 t5 \' t/ a5 d◆ 8-bit / 10-bit / 12-bit A/D converter
+ r- h/ ~- m9 j* l @: h' U◆ CDS / PGA function 0 dB to 24 dB: Analog Gain (0.1 dB step) 24.1 dB to 48 dB: Analog Gain: 24 dB + Digital Gain: 0.1 dB to 24 dB (0.1 dB step) 8 X: p9 C: x# ~ i
◆ I/O interface Low voltage LVDS (150 mVp-p) serial (4 ch / 8 ch / 16ch switching) DDR output % ~$ l6 r+ D9 [7 H+ R& G5 r
◆ Recommended lens F number: 2.8 or more (Close side) : d3 H4 c4 I. R9 P
◆ Recommended exit pupil distance: –100 mm to –∞3 e. _6 }. T" x1 e, S1 D
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|Shenzhen Lianshi Electronics Co., Ltd
( 粤ICP备13003189号 )
发表于 2022-3-29 21:22:13